technical data rev. 00 8-bit serial or parallel-input/ serial-output shift register high-performance silicon-gate cmos the IN74HC166A is identical in pinout to the ls/als 166. the device inputs are compatible with standard cmos outputs; w ith pullup resistors, they are compatible with ls/alsttl outputs. this device is a parallel-in or serial-in, serial-o ut shift register with gated clock inputs and an overriding clear input. t he shift/load input establishes the parallel-in or serial-in mode. when high, this input enables the serial data input and couples the eight flip-fl ops for serial shifting with each clock pulse. synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are e nabled. serial data flow is inhibited during parallel loading. clocking is d one on the low-to-high level edge of the clock pulse via a two input posit ive nor gate, which permits one input to be used as a clock enable or c lock inhibit function. clocking is inhibited when either of the clock inpu ts are held high, holding either input low enables the other clock in put. this will allow the system clock to be free running and the register st opped on command with the other clock input. a change from low-to-hi gh on the clock inhibit input should only be done when the clock in put is high. a buffered direct clear input overrides all other inp uts, including the clock, andsets all flip-flop to zero. ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices IN74HC166A ordering information IN74HC166An plastic IN74HC166Ad soic t a = -55 to 125 c for all packages pin assignment logic diagram pin 16 =v cc pin 8 = gnd
IN74HC166A rev. 00 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package + 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damag e to the device may occur. functional operation should be restricted to the re commended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gn d) 0 v cc v t a operating temperature, all package types -55 +125 c t r , t f input rise and fall time (figure 1) v cc =2.0 v v cc =4.5 v v cc =6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard against damage due to high static voltages or elect ric fields. however, precautions must be taken to avoid applica tions of any voltage higher than maximum rated volt ages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
IN74HC166A rev. 00 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to -55 c 85 c 125 c unit v ih minimum high-level input voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low - level input voltage v out =0.1 v or v cc -0.1 v ? i out ? 20 a 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 v v oh minimum high-level output voltage v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il ? i out ? 4.0 ma ? i out ? 5.2 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low-level output voltage v in =v ih or v il ? i out ? 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in =v ih or v il ? i out ? 4.0 ma ? i out ? 5.2 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 a 6.0 8.0 80 160 a function table inputs internal outputs output clear shift/load clock inhibit clock s a parallel a...h q a q b q h l x x x x x l l l h x x x x no change h l l x a...h a b h h h l h x h q an q gn h h l l x l q an q gn h x h x x x no change x = don?t care a...h = the level of steady state input voltage at input a trough h respectively
IN74HC166A rev. 00 ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit f max minimum clock frequency (50% duty cycle) (figures 2 and 4) 2.0 4.5 6.0 6.0 31 36 5.0 25 28 4.2 21 25 mhz t plh , t phl maximum propagation delay, clock (or clock inhibit) to q h (figures 2,3 and 4) 2.0 4.5 6.0 140 28 24 175 35 30 210 42 36 ns t phl maximum propagation delay , clear to q h (figures 1 and 4) 2.0 4.5 6.0 150 30 26 200 40 34 230 48 40 ns t tlh , t thl maximum output transition time, any output (figures 1 and 4) 2.0 4.5 6.0 75 16 14 95 20 18 110 25 20 ns c in maximum input capacitance - 10 10 10 pf power dissipation capacitance (per package) typical @25 c,v cc =5.0 v c pd used to determine the no-load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 140 pf timing requirements (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit t su minimum setup time, shift/load to clock (figure 3) 2.0 4.5 6.0 80 16 14 100 20 18 120 24 20 ns t su minimum setup time, data before clock (or clock inhibit) (figure 3) 2.0 4.5 6.0 80 16 14 100 20 18 120 24 20 ns t w minimum pulse width, clock (or clock inhibit) (figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns
IN74HC166A rev. 00 figure 1. switching waveforms figure 2. switching waveforms figure 3. switching waveforms figure 4. test circuit
IN74HC166A rev. 00 timing diagram expanded logic diagram
IN74HC166A rev. 00 n suffix plastic dip (ms - 001bb) symbol min max a 18.67 19.69 b 6.1 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 gh j 0 10 k 2.92 3.81 notes: l 7.62 8.26 1. dimensions ?a?, ?b? do not include mold flash or pr otrusions. m 0.2 0.36 maximum mold flash or protrusions 0.25 mm (0.010 ) per side. n 0.38 d suffix soic (ms - 012ac) symbol min max a 9.8 10 b 3.8 4 c 1.35 1.75 d 0.33 0.51 f 0.4 1.27 gh j 0 8 notes: k 0.1 0.25 1. dimensions a and b do not include mold flash or pro trusion. m 0.19 0.25 2. maximum mold flash or protrusion 0.15 mm (0.006) pe r side p 5.8 6.2 for a; for b ? 0.25 mm (0.010) per side. r 0.25 0.5 5.72 2.54 7.62 1.27 dimension, mm dimension, mm a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 16 8 9 l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 16 8 9
|
